1. Field of the Invention
The invention pertains to an In-Plane switching (IPS) mode liquid crystal display (LCD) device, and more particularly, to a method for driving an IPS mode LCD device, to prevent a leakage current by a common voltage swing.
2. Discussion of the Related Art
Demand for various display devices have increased with the development of an information society. Accordingly, many efforts have been made to research and develop various flat display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), an electroluminescent display (ELD), and a vacuum fluorescent display (VFD). Some types of flat display devices have already been utilized as displays for various types of equipment.
Among the various flat display devices, liquid crystal display (LCD) devices find the most wide use due to the advantageous characteristics of thin profile, lightness of weight, and low power consumption. The LCD devices thus provide a substitute for a Cathode Ray Tube (CRT). In addition to mobile type LCD devices such as a notebook computer display, LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.
Despite various technical developments in the LCD technology for applications in different fields, research in enhancing the picture quality of the LCD device has been, in some respects, lacking as compared to other features and advantages of the LCD device. In order to use LCD devices in various applications as a general use display, the key to developing LCD devices depends on the LCD device producing a high quality picture, including high resolution and high luminance with a large-sized screen, while still maintaining lightness of weight, a thin profile, and low power consumption. Currently, active matrix-type LCD devices have been developed because of their high resolution and image quality, and these devices have thin film transistors and pixel electrodes are arranged in a matrix-type configuration.
In general, an LCD device includes an LCD panel for displaying an image and a driver for supplying a driving signal to the LCD panel. In addition, the LCD panel includes first and second substrates bonded to each other to have a cell gap therebetween. A liquid crystal layer is formed between the first and second substrates. The first substrate (TFT array substrate) includes multiple gate lines arranged along a first direction at fixed intervals, multiple data lines arranged along a second direction perpendicular to the first direction at fixed intervals, multiple pixel electrodes arranged in a matrix-type configuration within pixel regions defined by crossing of the gate and data lines, and multiple thin film transistors that are activated according to signals supplied to the gate lines for transmitting signals from the data lines to the pixel electrodes. Also, the second substrate (color filter array substrate) includes a black matrix layer that excludes light from portions of the first substrate except at the pixel regions, an R/G/B color filter layer for displaying various colors, and a common electrode for producing the image. A cell gap is maintained between the first and second substrates by spacers, and the first and second substrates are bonded together by a sealant. A liquid crystal is injected between the first and second substrates. Also, the driver for applying the signal to the LCD panel includes a gate driver for applying a scanning signal to the gate line, and a source driver for applying a signal to the data line. The gate and data drivers are controlled by a timing controller.
Driving the LCD device is in accordance to the optical anisotropy and the polarizing characteristics of the liquid crystal material. Liquid crystal molecules are aligned using directional characteristics, because the liquid crystal molecules have anisotropic long and thin shapes. An induced electric field controls the alignment direction of the liquid crystal molecules of the liquid crystal layer. Light irradiated through the liquid crystal layer may be accordingly controlled by the alignment direction of the liquid crystal molecules, thereby displaying the image.
As discussed above, if the pixel electrode is formed on the first substrate and the common electrode is formed on the second substrate, the liquid crystal layer is driven by an electric field perpendicular to the first and second substrates. Thus, it is difficult to obtain a wide viewing angle. However, an In-Plane Switching (IPS) mode LCD device drives the liquid crystal layer by using an electric field parallel to the first and second substrates, thereby providing a wide viewing angle. For example, along a frontal direction of the IPS mode LCD device, a viewer can have a viewing angle of 70° in all directions (i.e., lower, upper, left, and right directions). Compared to general TN (twisted nematic) mode LCD devices, IPS mode LCD devices have simplified fabrication process steps, and reduced color shift.
The related art In-Plane switching (IPS) mode LCD device will now be described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view schematically illustrating the related art IPS mode LCD device. As shown in FIG. 1, the related art IPS mode LCD device includes first and second substrates 1 and 2 being opposite to each other, and a liquid crystal material layer 3 between the first and second substrates 1 and 2. A thin film transistor (TFT) array is formed on the first substrate 1 in a matrix-type configuration. Although not shown, a drain electrode of the thin film transistor is connected to a pixel electrode 20, and a common electrode 30 is formed spaced apart from the pixel electrode 20. In addition, the second substrate 2 includes a black matrix layer (not shown) that prevents light leakage from portions of the first substrate 1 except where the pixel regions are located, and also includes a color filter layer for displaying various colors. In the related art IPS mode LCD device, the pixel electrode 20 and the common electrode 30 are formed along the same plane, whereby the liquid crystal layer is driven by an induced electric field parallel to the first and second substrates 1 and 2. FIG. 1 also shows a surface 10 of the substrate 1.
Driving the related art IPS mode LCD device will be described as follows. In the related art LCD devices including the IPS mode LCD device, respective pixels are arranged in a matrix-type configuration. That is, when a scanning signal is supplied to one gate line, a video signal is supplied to the pixel corresponding to the gate line. The liquid crystal material injected between the first and second substrates 1 and 2 may deteriorate when a DC voltage is applied for an extended period of time. In order to prevent this problem, the polarity of the supplied voltage is cyclically changed, which is commonly referred to as a polarity inversion method. The polarity inversion method is classified into a frame inversion method, a line inversion method, a column inversion method, and a dot inversion method.
In the frame inversion method, positive and negative polarities of data voltage are supplied to the liquid crystal material as a common electrode voltage being alternately supplied to each frame. For example, if a positive (+) polarity data voltage is supplied to an even frame, then a negative (−) polarity data voltage is supplied to an odd frame. Thus, the same polarity data voltage is supplied according to the even or odd frame, thereby decreasing consumption current during the switching mode. However, the frame inversion method is sensitive to flicker generated according to an asymmetrical transmittance between the positive and negative polarities. In addition, the frame inversion method is susceptible to crosstalk caused by interference between data signals of adjacent pixels.
The line inversion method finds common use in low-resolution devices (i.e., VGA (video graphic array) and SVGA (super video graphics array) devices), in which a data voltage is supplied such that the polarity of data voltage supplied to the liquid crystal material for a common electrode voltage is changed according to a vertical direction. For example, in a first frame, a positive (+) polarity data voltage is supplied to an odd gate line, and a negative (−) polarity data voltage is supplied to an even gate line. Next, in a second frame, the negative (−) polarity data voltage is supplied to the odd gate line, and a positive (+) polarity data voltage is supplied to the even gate line. In the line inversion method, the polarities of the data voltage are oppositely supplied to adjacent lines such that the luminance difference is offset between the lines according to spatial averaging, thereby preventing flicker during frame inversion. For example, the opposite-polarity data voltages are supplied along a vertical direction, whereby a coupling phenomenon of the data signals is offset, thereby decreasing vertical crosstalk during the frame inversion. However, the polarity of the data voltage is the same along a horizontal direction, so that horizontal crosstalk is generated, and consumption current increases due to an increase of the number of switching operations, as compared with that during the frame inversion.
In the column inversion method, the same polarity of data voltage supplied to liquid crystal material for a common electrode voltage is supplied in the vertical direction, and positive and negative polarities of the data voltage are alternately supplied along the horizontal direction. It is thus possible to both minimize flicker by spatial averaging and to minimize horizontal crosstalk. However, the column inversion method requires a high-voltage column drive IC because the opposite-polarity data voltages are supplied to the adjacent lines according to the vertical direction.
The dot inversion method finds applications in high-resolution devices (i.e., XGA (extended graphics array), SXGA (super extended graphics array), and UXGA (ultra extended graphics array) devices) for obtaining the greatest quality picture image. In the dot inversion method, the polarity of data voltage is differently supplied to all-direction adjacent pixels. It is accordingly possible to minimize flicker by spatial averaging. However, the dot inversion method is problematic since the dot inversion method uses a high-voltage driver that results in a high consumption current.
The related art IPS mode LCD device of the dot inversion method will now be described. FIG. 2 shows a layout of a pixel of the related art IPS mode LCD device. FIG. 3 depicts a cross-sectional view taken along line I-I′ of FIG. 2. FIG. 4 shows a cross-sectional view taken along line II-II′ of FIG. 2.
Referring to FIG. 2, the related art IPS mode LCD device includes multiple gate and data lines 40 and 50 crossing each other to define multiple pixel regions, multiple common lines 60 spaced apart from the multiple gate lines 40, multiple thin film transistors (TFT) respectively formed at crossing portions of the multiple gate and data lines 40 and 50, multiple pixel electrodes 20 connected with respective drain electrodes of the thin film transistors and arranged as a “1-shaped” region within pixel regions, and a common electrode 30 formed as an “inverted U-shaped” spaced apart from the pixel electrode 20 within the pixel region and connected with the common line 60.
A method for manufacturing a related art IPS mode LCD device can be described with reference to FIG. 3 and FIG. 4. First, a metal layer is deposited on an entire surface of a substrate 10, and then it is selectively removed to thereby form both the gate line 40 having a gate electrode projected along a horizontal direction, and the common line 60 along the same direction as the gate line 40 and spaced apart by a predetermined interval from the gate line 40. Then, a gate-insulating layer 25 is formed on the entire surface of the substrate 10 including the gate line 40 and the common line 60. A semiconductor layer (not shown) is subsequently formed on the gate-insulating layer 25 above the gate electrode. Then, a metal layer is formed on the substrate 10 including the gate insulating layer 25 and the semiconductor layer, and then selectively removed to form the data line 50 perpendicular to the gate line 40 and source/drain electrodes 50c. Accordingly, a thin film transistor (TFT) having a gate electrode, a semiconductor layer, and source/drain electrodes 50c is formed on the substrate 10.
Next, a passivation layer 35 is formed on the entire surface of the substrate 10 including the data line 50, and contact holes are formed in the passivation layer 35 corresponding to the drain electrode 50c of the TFT and a predetermined portion of the common line 60. A metal layer is then deposited on an entire surface of the passivation layer 35, and patterned to form the pixel electrode 20 that connects to the drain electrode 50c of the TFT, and the common electrode 30 that connects to the common line 60 spaced apart from the pixel electrode 20. The common electrode 30 is accordingly in contact with the underlying common line 60 to provide power to the common electrode 30. A data voltage is also supplied to the pixel electrode 20 according to a conductive state of the TFT. In addition, the common lines 60 connect to one another, and the same common voltage signal Vcom (which is a DC voltage) is applied to the common lines 60.
FIG. 5 shows a circuit diagram equivalent to that of FIG. 2. FIG. 6 depicts a timing diagram of the pixel voltage according to each gate line. FIG. 5 shows a unit pixel of the related art IPS mode LCD device, and a storage capacitor Cst is formed between the storage line 60 and the drain electrode 50c of the TFT formed between of the gate and data lines 40 and 50. A liquid crystal capacitor CLC is then formed between the pixel electrode 20 and the common electrode 30, and the storage capacitor Cst is connected in parallel to the liquid crystal capacitor CLC.
FIG. 6 shows that the common voltage Vcom signal is maintained at a constant level even though the signal voltage of the pixel or the gate line 40 is changed, or the frame is changed. In this state, the common voltage Vcom signal maintains an intermediate level between two level voltages applied to the data lines. The polarity of the voltage applied to the data line is inversely applied to the respective pixels in the horizontal direction. That is, the data voltage is applied such that positive (+) and negative (−) polarities for the Vcom are inversely applied to the respective pixels by alternately applying positive (+) and negative (−) polarity data voltages to the data lines crossing the gate lines. The same polarity of the data voltage is applied at this time to respective odd data lines, or respective even data lines.
In order to drive the corresponding pixel, a gate driver (not shown) applies a selected pulse through the gate line, and a source driver (not shown) applies a video signal to the thin film transistor turned on by a signal line. By applying the data voltage by the turned-on thin film transistor, the liquid crystal capacitor CLC and the storage capacitor Cst connected between the drain electrode of the thin film transistor and the common line are charged during the turning-on of the thin film transistor. After turing-off the thin film transistor, electric charges are maintained until the thin film transistor is turned-on. Therefore, when the thin film transistor is turned-on, the data voltage is applied to the pixel electrode through the thin film transistor and is charged into the liquid crystal capacitor and the storage capacitor. Also, the data voltage is not applied to the pixel electrode when the thin film transistor is turned off, and electric charges of the data voltage are maintained by the liquid crystal capacitor and the storage capacitor until the thin film transistor is turned-on.
FIG. 6 shows a pixel voltage that is changed by a difference amount ΔVp according to a parasitic capacitor Cgs formed between the gate and source electrodes of the thin film transistor along a falling edge of the scanning signal supplied to the gate line, whereby the difference amount ΔVp induces an alignment direction of the liquid crystal material.
FIG. 7 shows a view illustrating a polarity change for a common voltage in respective pixels according to odd frame/even frame of a related art IPS mode LCD device. Referring to FIG. 7, when the dot inversion method drives the IPS mode LCD device, polarity (i.e., data voltage for common voltage) is inversely supplied to adjacent pixels so that the polarities of the adjacent pixels are opposite to each other. Whenever the frame is changed, the polarity of the pixel inverts. For example, the polarity of the pixel alternately changes to a positive (+) and negative (−) state different from the polarity of the adjacent pixel, thereby obtaining a high-quality picture image.
FIG. 8 shows a block diagram illustrating the inside of a gate driver in a related art IPS mode LCD device. FIG. 9 shows a view illustrating a TCP structure of a gate driver, and a timing diagram illustrating input/output signal changes on the TCP structure in a related art IPS mode LCD device.
FIG. 8 shows a gate driver of the related art IPS mode LCD device that includes a shift register part 61, a level shifter 62, and a buffer 63. The shift register part 61 includes multiple shift registers receiving a Gate Start Pulse signal GSP, a Gate Shift Clock signal GSC, and a Left/Right select signal L/R from a timing controller, whereby the shift registers are sequentially operated. Also, the level shifter 62 receives a Gate Output Enable signal (GOE) from the timing controller, and sequentially shifts the signals. The buffer 63 outputs signals for the gate lines (Gout1, Gout2, . . . , Goutn) that are supplied to the gate lines as one state selected from VGH, VGL, VCC and VSS levels.
Operation of the gate driver will be described with reference to FIG. 9. First, the shift register part 61 shifts the GSP signal by using the GSC signal, thereby sequentially enabling the gate lines. After completing enabling of the gate lines during one frame, a carry value is carried so that the gate lines of a second frame are enabled. Subsequently, the level shifter 62 sequentially level-shifts the signals supplied to the gate lines, and outputs the level-shifted signals to the buffer 63. Accordingly, the multiple gate lines connected to the buffer 63 are sequentially enabled. At this time, a predetermined gate line synchronized by the GSC signal is maintained at the VGH level, and then the predetermined gate line is maintained at the VGL level along a rising edge of the GOE signal.
Driving the related art IPS mode LCD device having the aforementioned gate driver will be described as follows. First, the source driver (not shown) sequentially receives video data signals of the respective pixels from the timing controller, and stores the video data signals corresponding to the respective data lines. Then, the gate driver sequentially supplies the scanning signals to the multiple gate lines by outputting the Gate Shift Clock signal (GSC), the Gate Shift Pulse signal (GSC), and the Gate Output Enable signal (GOE). Accordingly, the multiple thin film transistors connected to the selected gate line turn ON, whereby the video data signals (i.e., data voltage type) output from the source driver are supplied to the drain electrode of the thin film transistor to thereby display the video data on an LCD panel. Repetitive performance of the aforementioned process steps display the video data on the LCD panel. In this case, multiple pins from ‘1’ to ‘n’ are sequentially formed at an output side of a gate driver Tape Carrier Package (TCP) to output signals for the gate lines.
However, the related art IPS mode LCD device has many disadvantages, some of which are described below.
When driving the related art IPS mode LCD device using the dot inversion method, a constant value is supplied to the common voltage signal in a DC state, and the positive (+) and negative (−) polarity data voltages for the common voltage signal are alternately supplied to the data lines of the respective pixels. The pixel voltage supplied to the liquid crystal accordingly has a polarity dependent on the data voltage, and it is necessary to use a source driver having a great output voltage difference in order to induce a high voltage to the liquid crystal material. The source driver of the IPS mode LCD device generally has an extended output using a constant voltage VDD power source of 15V. The pixel voltage supplied to the liquid crystal material is accordingly about (−)6V or (+)6V. However, since a source driver having a high output value is expensive, it has been necessary to obtain low power consumption by lowering the output value to thereby decrease manufacturing costs.
In an IPS mode LCD device, the liquid crystal material is driven according to a fringe field formed between the pixel electrode and the common electrode. It is accordingly necessary to form a fringe field having a great value by narrowing the interval between the pixel electrode and the common electrode. In order to narrow the interval between the pixel electrode and the common electrode, it becomes necessary to pattern the pixel and common electrodes to have a finger-type crossing at a predetermined interval. However, if the interval between the pixel electrode and the common electrode becomes narrow, then the aperture ratio of the pixel deteriorates. To improve the aperture ratio, the pixel or common electrode may be formed of a transparent material such as indium-tin-oxide (ITO). However, patterns having various shapes are formed within the pixel region so that it is difficult to uniformly transmit the light. When widening the interval between the pixel electrode and the common electrode for improving the aperture ratio, the electric field parallel to the substrates decreases between the pixel electrode and the common electrode. Thus, in order to obtain the required luminance, the output of the data voltage must be increased.